AMD Next Horizons Announced

Yeah, but don't expect this to guarantee 16-core desktop processors on AM4. This just makes it easier to offer 64-core EPYC.

They can easily release the Zen 2 R7 as single-CCX. If the promised IPC improvements are there, it will sell itself.

But it would be painless to go back to dual-CCX 16-core r7 series. They may save that for a 2020 platform refresh.

i don't think we'll see 16 core on am4 personally but i think the chiplet design may be used for threadripper to solve the current issues the WX chips have. but we probably won't find out til CES 2019.
 
yes 14nm IO die plus 8 1x8 core 7nm dies/chiplets around it. lisa showed the processor on stage.

they showed a couple demo's.. did a single socket rome vs dual 8180 platinums in c-ray.. beat it by 2 seconds. they won't announce yet what the clock speeds are since they haven't made them official yet.
Dual vs single socket... holy fuck AMD bought the serious pwnage. Now Intel will have to glue two of their massive dies together to even begin to consider competing (as they already released yesterday to crickets lol). I bet they will have horrible die-die latencies depending on the workload and core.

8 core chiplets confirmed! ROFL! bumped up for 4core ccx. intel on suicide watch. ROFL!
Juan, Shintai and the IDF and co must be currently trying to slit their wrists with a pot handle.
Assad_Whiskey.jpg

Yeah, but don't expect this to guarantee 16-core desktop processors on AM4. This just makes it easier to offer 64-core EPYC.

They can easily release the Zen 2 R7 as single-CCX. If the promised IPC improvements are there, it will sell itself.

But it would be painless to go back to dual-CCX 16-core r7 series. They may save that for a 2020 platform refresh.

Yeah I don't see this enabling cheap multi chiplet Ryzen dCPUs when they need to use multiple chiplets. Maybe on high end but can they support that in AM4? Memory bandwidth is my concern, like the 2990.
Packaging one die like a normal CPU (but with an active interposer die) isn't going to change much bar slightly higher BOM and processing costs. When you add multiple chiplets is where it gets expensive and more difficult and higher error rate.
The cache and IO on the 1x8 core design is going to be the kicker here, IMC tweaks will help.

9900k is going to be forever cemented as a hot POS in ~6 months or however long it takes to get to desktop market. Can you imagine that they can probably do about 105% of the performance with half the power? It's like Zen vs 7900 series CPU for efficiency all over again... except this time AMD wins in every front, performance, power, efficiency and likely OCability after the strung out, Fiji-style 9900k.
 
i don't think we'll see 16 core on am4 personally but i think the chiplet design may be used for threadripper to solve the current issues the WX chips have. but we probably won't find out til CES 2019.

They'll also solve the ccx latency issues on AM4 would the not :)? I think we will see either 12 or 16 core desktop chips as well. Making 8 core a mainstream option. AMD is going to have a good year.
 
Dual vs single socket... holy fuck AMD bought the serious pwnage. Now Intel will have to glue two of their massive dies together to even begin to consider competing (as they already released yesterday to crickets lol). I bet they will have horrible die-die latencies depending on the workload and core.


Juan, Shintai and the IDF and co must be currently trying to slit their wrists with a pot handle.
View attachment 118036



Yeah I don't see this enabling cheap multi chiplet Ryzen dCPUs when they need to use multiple chiplets. Maybe on high end but can they support that in AM4? Memory bandwidth is my concern, like the 2990.
Packaging one die like a normal CPU (but with an active interposer die) isn't going to change much bar slightly higher BOM and processing costs. When you add multiple chiplets is where it gets expensive and more difficult and higher error rate.
The cache and IO on the 1x8 core design is going to be the kicker here, IMC tweaks will help.

9900k is going to be forever cemented as a hot POS in ~6 months or however long it takes to get to desktop market. Can you imagine that they can probably do about 105% of the performance with half the power? It's like Zen vs 7900 series CPU for efficiency all over again... except this time AMD wins in every front, performance, power, efficiency and likely OCability after the strung out, Fiji-style 9900k.

from the presentation, the move to the 14nm io + chiplet design will increase memory bandwidth.. each chiplet can talk to each other while also accessing the io chip. in theory this should remove the latency issue that current ryzen has where each die couldn't directly access the other dies memory lanes without transfering what it was working on to that die but i'll admit most of this is well over my head, i'm just going off of what Lisa and the other guy was talking about. it'll be interesting to see what information the reports get out of the hands on demo stuff coming up in about 30-40 minutes.
 
They'll also solve the ccx latency issues on AM4 would the not :)? I think we will see either 12 or 16 core desktop chips as well. Making 8 core a mainstream option. AMD is going to have a good year.

who knows. But I think they will start off with 8 core chips or maybe 16 core chips. But 8 core seems highly likely and then go up and down from there as the time goes on.
 
I think they will role with 8 core single die for desktops first. I am not sure how they will do 12 core if the single die is 8 core? They will likely have to stay within 8 core chiplets. They might release 16 core ryzen later in the year. Or they might just keep the 16-24-32-48 cores for threadripper. I think for now 8 core seems to be fine. But then again I wouldn't be surprised if they release 16 core ryzen 2 chips and charge a premium for it and knowing intel can't match it to gain market share. Its hard to imagine AMD having so many options on the CPU side lol. Good for them!

maybe bring back the x800x name.. so the 3800/x are the halo 16 core chips on am4 which i agree will cost a premium just to say they can do it even if it makes no sense.. 3700x and lower are the 4/6/8 cores. personally though if the difference of having more cores = lower clocks i'd rather have less cores and higher clocks..
 
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who knows. But I think they will start off with 8 core chips or maybe 16 core chips. But 8 core seems highly likely and then go up and down from there as the time goes on.

They'd do 12 core the same way they do current 6 cores :p chips that did not yield 8 fully functional cores
 
Wow talka bout impressive! Cannot wait to upgrade to a 3k series next year. So nice knowing I dont have to upgrade my motherboard!
 
Wow talka bout impressive! Cannot wait to upgrade to a 3k series next year. So nice knowing I dont have to upgrade my motherboard!

Yep unless you really need PCI-e 4.0 I don't see any point. I'll be rocking my x470.
 
yes 14nm IO die plus 8 1x8 core 7nm dies/chiplets around it. lisa showed the processor on stage.

they showed a couple demo's.. did a single socket rome vs dual 8180 platinums in c-ray.. beat it by 2 seconds. they won't announce yet what the clock speeds are since they haven't made them official yet but they think they may be able to get them higher than current prototype chips..


were are these demos at? i can not find them in the video. Does this mean 64 core Thread rippers in a few years?
 
It's funny to think where this all started back some years ago..
AMD-Radeon-Fury-Fiji-Feature-Image.jpg
 
Looks a little different than I expected. I expected to see the chiplets ringing the I/O chip

Zen2-Rome Epyc.jpg

But it looks badass all the same. To think each of those little chis is 8 cores. I guess the current water block fin strategies for cooling the future threadripper version of that would work as well as it does today.
 
Looks a little different than I expected. I expected to see the chiplets ringing the I/O chip

View attachment 118098

But it looks badass all the same. To think each of those little chis is 8 cores. I guess the current water block fin strategies for cooling the future threadripper version of that would work as well as it does today.

So gonna have one of these on my key-ring in 20 years. Delidded, of course.
 
Based on epyc being 8 channel ram, i'm thinking each 8 core chiplet is meant to access a ram channel, which would mean 2 chiplets for ryzen.

Also, could the io chip also include an (optional) igp? Even a 3 CU vega would be plenty, and that io chip is pretty big...
 
They'll also solve the ccx latency issues on AM4 would the not :)? I think we will see either 12 or 16 core desktop chips as well. Making 8 core a mainstream option. AMD is going to have a good year.

But there is no way to not have latency it is in every design. Even the one that uses a single die and lots of cores.
The only time it really manifested itself was when you would run high framerate 1080p stuff. If you game at higher resolutions you would not encounter it or in lesser form.
 
But there is no way to not have latency it is in every design. Even the one that uses a single die and lots of cores.
The only time it really manifested itself was when you would run high framerate 1080p stuff. If you game at higher resolutions you would not encounter it or in lesser form.

Latency exists as long as we exist in the space time continuum unless were talking about some fancy 500 years from now quantum entanglement tech.
 
Based on epyc being 8 channel ram, i'm thinking each 8 core chiplet is meant to access a ram channel, which would mean 2 chiplets for ryzen.

Also, could the io chip also include an (optional) igp? Even a 3 CU vega would be plenty, and that io chip is pretty big...


as far as my understanding with rome the chiplets are not directly connected to the ram.. the chiplets connect to each other and the IO chip in the center which is then connected to everything else. that was how they were able to add 8 cores to each one. i could be wrong though.
 
*throws wads of Euros against the screen*
What are you talking about "3rd Gen Ryzen not out yet"? I hear the words, I don't understand.
*continues to throw money at the screen*
 
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Looks a little different than I expected. I expected to see the chiplets ringing the I/O chip

View attachment 118098

But it looks badass all the same. To think each of those little chis is 8 cores. I guess the current water block fin strategies for cooling the future threadripper version of that would work as well as it does today.

As I said to Chia (the guy that draw those Rome diagrams circulated by the Internet during last weeks), enclosing the IO die with all the core dies would give problems with wiring. The IO is for communicating the chip with the surrounds, so enclosing it at the center was the worst location possible.

Interesting as well that the core dies are coming in groups of two, with four dies closer to the IO die, and four dies away.

NAPLES vs ROME side by side

o4d30iW.png
 
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As I said to Chia (the guy that draw those Rome diagrams circulated by the Internet during last weeks), enclosing the IO die with all the core dies would give problems with wiring. The IO is for communicating the chip with the surrounds, so enclosing it at the center was the worst location possible.

Interesting as well that the core dies are coming in groups of two, with four dies closer to the IO die, and four dies away.

NAPLES vs ROME side by side

View attachment 118257

Come on, kill our hype damnit!
 
As I said to Chia (the guy that draw those Rome diagrams circulated by the Internet during last weeks), enclosing the IO die with all the core dies would give problems with wiring. The IO is for communicating the chip with the surrounds, so enclosing it at the center was the worst location possible.

Interesting as well that the core dies are coming in groups of two, with four dies closer to the IO die, and four dies away.

NAPLES vs ROME side by side

View attachment 118257
Just have the traces on separate layers and the two dies next to each other be mirrors (or rotate one 180°), then the electrical length would be nearly identical. Not nearly as bad as you're making it out to be.

Edit: oh, you're talking about the hypothetical layout. You confused me because you didn't include that image. Yeah, that'd be a clusterfuck.
 
Seems to me the I/O chip is acting as a silicon version of IF for I/O between chiplets. Personally I am waiting very impatiently to see how this architecture stacks up against Intel's finest which as of a couple days ago seems to be a 56 core proc. I have a feeling Rome will beating Intel up and taking their lunch money.
 
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Seems to me the I/O chip is acting as a silicon version of IF for I/O between chiplets. Personally I am waiting very impatiently to see how this architecture stacks up against Intel's finest which as of a couple days ago seems to be a 56 core proc. I have a feeling Rome will beating Intel up and taking their lunch money.

The problem for intel is that they can't compete on price, it's a lot , lot harder to make a single 28 core, or 56 core die without any defects, than it is to make 4 or 8 , 8 core dies.
 
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for Intel;'s 56 core chip they are following AMD's design of using more than one die under the heatspreader. Their 56-core chip is a pair of 28-core dies. But I agree that making large integrated dies is harder to do - esp if you don't go to a smaller process.
 
for Intel;'s 56 core chip they are following AMD's design of using more than one die under the heatspreader. Their 56-core chip is a pair of 28-core dies. But I agree that making large integrated dies is harder to do - esp if you don't go to a smaller process.

But, how are they connecting the 2 ? AMD can pull it off because of IF. Does intels UPI keep up for the requirements of 2 28 core dies :p?
 
The problem for intel is that they can't compete on price, it's a lot , lot harder to make a single 28 core, or 56 core die without any defects, than it is to make 4 or 8 , 8 core dies.
Same goes for efficiency and thermal management as we've already seen.
Some benchies vs current Epyc has them beating Xeon soundly while using 1/3rd less power...
That's going to be a painfully big gap with Epyc 2. Intel will be utterly out-performed and power hungry. They already smashed out the dual socket Xeons with a single socket Epyc, which is close to what this will be with Intel glue, so they already have em beat with ES... and we have not seen everything it will do yet I bet.
I'd love to see the power numbers for that benchmark. I bet AMD is close to 1/3rd less power at minimum now, not at just some applications. Maybe down to half the power of those enormous 28 core dies.
 
Same goes for efficiency and thermal management as we've already seen.
Some benchies vs current Epyc has them beating Xeon soundly while using 1/3rd less power...
That's going to be a painfully big gap with Epyc 2. Intel will be utterly out-performed and power hungry. They already smashed out the dual socket Xeons with a single socket Epyc, which is close to what this will be with Intel glue, so they already have em beat with ES... and we have not seen everything it will do yet I bet.
I'd love to see the power numbers for that benchmark. I bet AMD is close to 1/3rd less power at minimum now, not at just some applications. Maybe down to half the power of those enormous 28 core dies.

This is like the K7 and K8 days all over again :D awesome
 
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This is like the K7 and K8 days all over again :D awesome
Yes, I was going to liken it to the AXP but I feel the A64 was more of an ass-reaming as it took them 5 years to recover from that pounding xD, hence the OC.
This time maybe it'll take them 3-4 years. We will see, seems like the playing field of foundry is pretty level and will remain that way due to limitations. Same goes for GPUs in coming years.
By the time Intel has 10nm going beyond 65-70% yields, AMD will be running 5nm and with even smaller features and a better process.
Intel with their Cobalt looks like they were trying a Netburst.. clocks. But you can see that in the Intel fan crowd 'does it do 5ghz?' 'if it can't do 5ghz it's slow' etc. Someone on here was bitching about the lack of 5GHz 8 core CPUs so I linked them Bulldozer ^_^ GHz is not how people win the performance war any more and AMD has proven that yet again (in both ways, ironically)..
History sure does repeat though eh!

..Enjoy some OC to warm up ;)
View attachment 117968
 
i do expect a two chiplet + IO chip desktop CPU:
two DDR4 channels for two chiplets is well balanced vis-a-vis Rome.
Rome is specified as having 128 PCIE lanes, which is only 16 for each chiplet.

Yes, a shrunk desktop IO or southbridge could include some PCIE, but high end desktop currently has 20lanes, and i don't see that going down.
 
Just have the traces on separate layers and the two dies next to each other be mirrors (or rotate one 180°), then the electrical length would be nearly identical. Not nearly as bad as you're making it out to be.

Edit: oh, you're talking about the hypothetical layout. You confused me because you didn't include that image. Yeah, that'd be a clusterfuck.

Yes, I was talking about his hypothetical diagrams (which didn't make sense), not about the actual chip (which makes sense).
 
i do expect a two chiplet + IO chip desktop CPU:
two DDR4 channels for two chiplets is well balanced vis-a-vis Rome.
Rome is specified as having 128 PCIE lanes, which is only 16 for each chiplet.

Yes, a shrunk desktop IO or southbridge could include some PCIE, but high end desktop currently has 20lanes, and i don't see that going down.
 
It will take a good while before we hear more I guess the desktop version is a little different.
 
Looks a little different than I expected. I expected to see the chiplets ringing the I/O chip

View attachment 118098

But it looks badass all the same. To think each of those little chis is 8 cores. I guess the current water block fin strategies for cooling the future threadripper version of that would work as well as it does today.

Yep, kinda fun how the companies that went in early on good TR4/SP3 designs are going to reap some rewards from doing it right the first time. EK and the 400 places that rebrand Asetek/Coolit/whatever should take notice.
 
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