AMD rumoured to be creating consumer oriented 16 Core/32 Thread Ryzen CPU

Snowdog said:
So if you want a rumored Ryzen 16c x dual socket.

Why not a Ryzen 32 Core Single socket. Ryzen 32 core is not even a rumor.

How is
2 socket X 16C,

better than:
1 socket x 32C?
Click to expand...
Clock speed, 32c for either manufacturer is going to result in low clocks due to the heat that's is being generated. 2x16c allows higher clock speed while keeping cpu temps in check
 
Snowdog said:
So if you want a rumored Ryzen 16c x dual socket.

Why not a Ryzen 32 Core Single socket. Ryzen 32 core is not even a rumor.

How is
2 socket X 16C,

better than:
1 socket x 32C?
Click to expand...

Depends on the clock speeds and if the applications being run are sensitive to said clock speeds.


Let's take it a step further:
How is
1 socket x 32c (upcoming Ryzen)

better than
2 socket x64c (if Ryzen was SMP capable)?

...NUMA limitation excluded.
 
The gaming issues that were causing the Ryzen AM4 CPUs to behave erratically to say the least have been ironed out.
Click to expand...
I am happy with the Ryzen but this carrot on the stick crap needs to stop. I don't game at all anymore so I am not affected but I don't have a distorted reality on the gaming efficacy.
 
Takes time to get a new architecture dialed in. Thread affinity seems to be a problem with games. Apparently the adaptive prefetch does work. Games or tasks get faster with repeated runs.
 
Double the memory bandwidth (4 channels) and double de number of cores. That destroys everything Intel has on its catalog. What I would like to know is if doubling the memory channels implies a double bandwidth Infinity Fabric, instead of 32 Bytes/cycle, 64 Bytes/cycle. I'd also increase RAM frequency to have the best performance in any scenario :p
 
Filiprino said:
Double the memory bandwidth (4 channels) and double de number of cores. That destroys everything Intel has on its catalog. What I would like to know is if doubling the memory channels implies a double bandwidth Infinity Fabric, instead of 32 Bytes/cycle, 64 Bytes/cycle. I'd also increase RAM frequency to have the best performance in any scenario :p
Click to expand...

On throughput? Maybe. I think it will be a close tie if rumors of 8-core SKL beating 10-core BDW are true. On latency? Nope. This 16C has lower clocks than 1800X.

The quad-channel is obtained by joining two dies with dual-channel each. It is expected that IF was unchanged.
 
juanrga said:
On throughput? Maybe. I think it will be a close tie if rumors of 8-core SKL beating 10-core BDW are true. On latency? Nope. This 16C has lower clocks than 1800X.

The quad-channel is obtained by joining two dies with dual-channel each. It is expected that IF was unchanged.
Click to expand...
IF? What does Instruction Fetch have to do with the bandwidth between L3 and the memory controllers, and between the I/O hub and the memory controllers? and between core complexes?
 
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