It doesn't matter because in a market with limited options and competition, the bad PR amounts to nothing.
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NVIDIA Allegedly Moving Ampere to 7nm TSMC in 2021
- Thread starter polonyc2
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It doesn't matter because in a market with limited options and competition, the bad PR amounts to nothing.
And it's only bad PR with a very very small subset of their market.
It should amount to something interesting for amd if they can deliver a product with stock behind it
Sadly that is true, but morons always outnumber. Its why this crap only gets worse.
Not sure what you are trying to say there. Anyways a response from EVGA regarding 3000 series availability is this "in 15 years at EVGA, this product has the highest demand out of any of them that we've seen, but it doesn't have the lowest supply out of them." Granted that is only EVGA but probably rings true for the other board partners as well.
All you have to do is look at retail availability and numbers to see this isn't anything like a normal soft launch and the numbers I've seen from a few online retailers seem to back that up as well. Microcenter had a fraction of the units in stores that they normally do, Fry's is gone but used to get similar numbers per store, and Best Buy normally has a handful in each store and instead had so few that they only sold online.
It might have more demand than normal but nobody is buying them by the palate like they were for cryptomining so I don't believe that demand is anywhere near the peak levels that we've seen. They clearly wanted to beat AMD to market even though they didn't have enough stock for a normal launch, the reason doesn't really matter that much but it's going to be speculated on unless Nvidia levels with us which they won't(and probably shouldn't).
But also look at the AIB's direct sales also higher than before, could simply be they are holding more back to sell directly where they get more profit than shipping to the retail stores.
I haven't seen any evidence that they're shipping any more that way than normally and I don't think Nvidia would willingly choose to go that route since it's a bad look to not have reasonable availability at retail and if there's one thing Nvidia does well other than GPUs it's PR.
Well to date most AIB's only sold refurbished models from their websites and very few new models, this has changed with this launch. There is also the possibility that the AIB's are holding out for NVidia to announce the models with the increased memory, their profits on those models would be much greater so they may be reserving parts for that launch. But from the reports coming out of Samsung, say the 10nm node process that they are using is working as expected, granted that could mean they expected shit yields but I doubt NVidia would shoot itself in the foot and risk missing key delivery deadlines like that. The investors would eat them for breakfast if they pulled a stunt like that, well only if it backfires. If it works and the numbers go up they would be rewarded handsomely for it, but that's a lot of speculation. So let's just sit back and enjoy the clown show.
If you follow any of Samsungs ARM foundry news... the idea that their yields are less then great on a chip 10x larger then they normally fab seem very plausible. As their yields on 100-150nm arm chips seems to be suspect at the moment. They have jumped to 5nm from 8 and seem to only be producing mid range parts at 5 as well. Rumor is Qcom and Samsung have agreed to produce lower end 700 series at 8nm to make good on contract terms for the the higher end 875 qcom parts. I have a feeling in early December it will be clear those parts moved to TMSC as well. But who knows those are rumors right now as well. Samsung 5nm exynos chips have been showing up in the wild... but they seem to be very much mid range parts. Makes me wonder if Samsung expected issues and are going to once again buy chips for their higher end phones for North American markets... and use their own chips only in over seas markets.
I know it doesn't for sure mean anything in regard to their fab work with Nvidia. Still it seems likely to me if they are having issues with 120mm ARM wafer fabrication right now... the idea they are having issues with wafers with 850+mm chips seems pretty logical. Chips that size are never going to be easy to fabricate. The number of chips per wafer has to be abysmal, and the potential for defects to ruin half or more of the wafer has to be very high. Nvidia really needs 450mm wafers to become a thing. I mean how many fully functional chips could they be pulling off a 300mm wafer with that massive die size perhaps 40 or 50 at best would be my guess.
We have a pretty good guess as to what TMSC is charging this year for 7 and 5nm waffers.... and based on a 610nm 5mm Nvidia part TMSC would expect to turn out around 70 5nm parts at that size per wafer. At 7nm a chip that size would have yields more in the range of 40 chips.
https://www.tomshardware.com/news/t...aled-300mm-wafer-at-5nm-is-nearly-dollar17000
With that in mind... Samsung has to have both made Nvidia a great deal, as chances are they are best case only looking at 40-50 chips per wafer. And if they are even experiencing even the smallest uptick in defect rate that number could very quickly drop to 20-30 fully working chips per wafer.
If that is the case... and Samsung is charging for 8nm what TMSC charges for 10nm Nvidia is already looking at around $300 per working chip. That could very easily explain shortages imo. Nvidia would be willing to eat some losses to have something to ship verses AMD this round... but also not want to exactly produce millions of them at those prices either. It would make sense for them to move to TMSC next year... IF they can get 7nm production space (which they should with Apple moving to 5nm) and get a good price out of TMSC. Cause even there they are looking at north of $200 per chip. If in early 2021 they can get surplus 7nm space from TMSC and get costs down under $200... they could easily be looking at half the cost vs Samsungs 8nm... even with Samsung firesale pricing. At some point no matter how good a deal Samsung makes... if they really are only pulling 40-50 fully operational chips off a wafer the costs will be what they are. Wafers aren't free.
I know it doesn't for sure mean anything in regard to their fab work with Nvidia. Still it seems likely to me if they are having issues with 120mm ARM wafer fabrication right now... the idea they are having issues with wafers with 850+mm chips seems pretty logical. Chips that size are never going to be easy to fabricate. The number of chips per wafer has to be abysmal, and the potential for defects to ruin half or more of the wafer has to be very high. Nvidia really needs 450mm wafers to become a thing. I mean how many fully functional chips could they be pulling off a 300mm wafer with that massive die size perhaps 40 or 50 at best would be my guess.
We have a pretty good guess as to what TMSC is charging this year for 7 and 5nm waffers.... and based on a 610nm 5mm Nvidia part TMSC would expect to turn out around 70 5nm parts at that size per wafer. At 7nm a chip that size would have yields more in the range of 40 chips.
https://www.tomshardware.com/news/t...aled-300mm-wafer-at-5nm-is-nearly-dollar17000
With that in mind... Samsung has to have both made Nvidia a great deal, as chances are they are best case only looking at 40-50 chips per wafer. And if they are even experiencing even the smallest uptick in defect rate that number could very quickly drop to 20-30 fully working chips per wafer.
If that is the case... and Samsung is charging for 8nm what TMSC charges for 10nm Nvidia is already looking at around $300 per working chip. That could very easily explain shortages imo. Nvidia would be willing to eat some losses to have something to ship verses AMD this round... but also not want to exactly produce millions of them at those prices either. It would make sense for them to move to TMSC next year... IF they can get 7nm production space (which they should with Apple moving to 5nm) and get a good price out of TMSC. Cause even there they are looking at north of $200 per chip. If in early 2021 they can get surplus 7nm space from TMSC and get costs down under $200... they could easily be looking at half the cost vs Samsungs 8nm... even with Samsung firesale pricing. At some point no matter how good a deal Samsung makes... if they really are only pulling 40-50 fully operational chips off a wafer the costs will be what they are. Wafers aren't free.
Why would yields be worse on an even older process?
Well it being more 10mn then 7 would explain the insane size of the chips. 862mm is a massive die size to try and fabricate.
The smaller the fab size the more you can pack in... at 862mm it does seem unlikely its 8nm in a way we would think of as being "almost" 7nm. 2080 chips where 775mm. (and where to large to deliver good yield numberss) Big navi is rumored to be 536mm.
When you fab a wafer of chips you are going to have a expected number of defects. If your wafer has 200 chips on it in the case of something the size of big navi you can expect to end up with 140-160 properly fully working chips... and probably 20-30 you can salvage fusing off CUs. Of course that depends how aggressive the designers are on clock rate goals... depending on the targets there its possibly only a fraction of the fully working chips (or all of them) hit those targets. At 862mm... the chances of some sort of defect hitting darn near every chip is very very high. The yields on massive dies suck its just physics. This is one reason AMD went to chiplets on the CPUs... it keeps cost down in 2 ways, reducing the size on the newest most expensive process of course, but also it greatly reduces the number of defective chips on a wafer. The same number of defects will "touch" fewer parts.
At 862mm squared the number of dies is very small per wafer. A 2080 TI wafer with 775mm chips each wafer is a max of 64 dies... with defect rate you could probably cut 10-20% off that number for working dies... and probably only a handful of those chips where both fully working and capable of hitting Clock targets. Cost per fully functioning parts was probably north of $200 each... even after recouping some some cost selling the defects as lower clocked/fused parts for lower end skus. At 862mm2 a 12" (300mm) can only hold a max 58 dies.... the defect rate HAS to be higher, more surface area means more chips will be touched by defects. Defects tend to be randomly scattered on the surface of a wafer.
The only way Ampere is cheaper to fab for Nvidia is if Samsung gave them an absolute insane deal on the fabrication. The problem is the die size and logical defect rate increase has to effect production time.
Didn't mean to write another book. Simply trying to say... physics are physics yields go down as chip surface increases. There is no way to get around that... even if Samsung has their 8nm process they are using nailed down and as perfect as could be. It will still produce an expected number of defects... which can only reduce yield when die size increases. Without question the yield of this generation NV chip is lower then the previous gen. Which was known to be an issue.
If Nvidia does switch to TMSC with Ampere I am sure it will be some form of super variant where they try really hard to squeeze that die size down into the 600mm range. It drastically reduces cost per chip.
To get to what bluestang said that it would mean worse yields. It would in that it would have incrased the die size. We know the size is 862mm... had Samsung had a working 7nm part the die would have probably came in more in the mid 600s. Which logically would have improved yields simply by having random defects touch fewer chips on the wafer. As a crazy thought... you could fab something like Ampere say at 12nm, it would simply mean the same design would end up being 1000mm or there about... you would get 30 or so chips on a wafer and probably 90% of them would be paperweights.
lol
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The physical size of each die doesn’t affect the number of defects per wafer but it does affect the total die yield. All else equal a 10nm wafer should have fewer defects than a 7nm wafer based on process maturity. Of course we have no idea what the actual defect rates are.
Of course physical size effects yield. Think about it... a die is going to have a specific amount of defects no matter how good your process is. They are spread randomly on the wafer. Like someone hit it with a scatter spray. If you have say 100 major defects on a wafer. If you have 200 chips lined up on it chances are high there will be plenty of chips with zero defects. If you only have 100 chips twice the size lined up the chances are double that each chip will be hit with a defect.
If you put a picture on a dart board and throw 100 random darts at it.... a wallet size picture would get hit less then a 8x10.
Large dies get hit with more random defects... its simple probability. More die size. More potential for defects to hit it.
Process maturity or no.... every fabrication process has a defect rate. Mature process of course have a lower defect rate but its never zero. And with massive die sizes like the ones NV is dealing with even a relatively low defect rate is going to lead to a pretty high overall defect rate.
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Axman
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Fewer defects doesn't necessarily mean a better yield unless the density increase outstrips the defect rate. So even though a smaller process might have more defects per wafer, it may still yield more dies without defects. It just depends.
DooKey
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The more mature the process usually equals less defects per wafer.
Axman
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And you also get more chips per wafer with a denser process.
Yep.
Which is what I said.
mpineda1110
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If Nvidia were to technically do this, would it mean a new version (super) or just a different version (version 2) of the 30xx series?
Axman
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They're sorta trying to kill off the many different brands. I half expect the double memory models to be "Super."