AMD X570 Chipset Blockdiagram Surfaces - Specs - PCIe 4.0 All The Way!

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[Update] - added new graphic, possible official AMD slide.

Source 1

Source 2

"AMD X570 is the company's first in-house design socket AM4 motherboard chipset, with the X370 and X470 chipsets being originally designed by ASMedia. With the X570, AMD hopes to leverage new PCI-Express gen 4.0 connectivity of its Ryzen 3000 Zen2 "Matisse" processors."

"On the AM4 "Valhalla" platform, the SoC puts out a total of 24 PCI-Express gen 4.0 lanes. 16 of these are allocated to PEG (PCI-Express graphics), configurable through external switches and redrivers either as single x16, or two x8 slots. Besides 16 PEG lanes, 4 lanes are allocated to one M.2 NVMe slot. The remaining 4 lanes serve as the chipset bus. With X570 being rumored to support gen 4.0 at least upstream, the chipset bus bandwidth is expected to double to 64 Gbps.

Since it's an SoC, the socket is also wired to LPCIO (SuperIO controller). The processor's integrated southbridge puts out two SATA 6 Gbps ports, one of which is switchable to the first M.2 slot; and four 5 Gbps USB 3.x ports. It also has an "Azalia" HD audio bus, so the motherboard's audio solution is directly wired to the SoC. Things get very interesting with the connectivity put out by the X570 chipset."

Am I seeing this correctly, so up to 3 32Gbps M.2 slots? Two possible from the chipset, one from CPU?

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Source 1

Source 2

"AMD X570 is the company's first in-house design socket AM4 motherboard chipset, with the X370 and X470 chipsets being originally designed by ASMedia. With the X570, AMD hopes to leverage new PCI-Express gen 4.0 connectivity of its Ryzen 3000 Zen2 "Matisse" processors."

"On the AM4 "Valhalla" platform, the SoC puts out a total of 24 PCI-Express gen 4.0 lanes. 16 of these are allocated to PEG (PCI-Express graphics), configurable through external switches and redrivers either as single x16, or two x8 slots. Besides 16 PEG lanes, 4 lanes are allocated to one M.2 NVMe slot. The remaining 4 lanes serve as the chipset bus. With X570 being rumored to support gen 4.0 at least upstream, the chipset bus bandwidth is expected to double to 64 Gbps.

Since it's an SoC, the socket is also wired to LPCIO (SuperIO controller). The processor's integrated southbridge puts out two SATA 6 Gbps ports, one of which is switchable to the first M.2 slot; and four 5 Gbps USB 3.x ports. It also has an "Azalia" HD audio bus, so the motherboard's audio solution is directly wired to the SoC. Things get very interesting with the connectivity put out by the X570 chipset."

Am I seeing this correctly, so up to 3 32Gbps M.2 slots? Two possible from the chipset, one from CPU?

View attachment 162093

Hmm. Interesting.

I thought the SoC would put out 28 lanes.

Isnt that how Ryzen 1000 and 2000 series CPU's worked?

28 total - 4 for chipset uplink = 24 availaböe direct to CPU? Or did I misunderstand the older designs?

With up to 40 lanes sharing the bandwidth on the chipset, even at Gen4, 4 lanes seems a little anemic. I was hoping they had upped it to 8.
 
Hmm. Interesting.

I thought the SoC would put out 28 lanes.

Isnt that how Ryzen 1000 and 2000 series CPU's worked?

28 total - 4 for chipset uplink = 24 availaböe direct to CPU? Or did I misunderstand the older designs?

With up to 40 lanes sharing the bandwidth on the chipset, even at Gen4, 4 lanes seems a little anemic. I was hoping they had upped it to 8.
Will probably be just okay with most devices being 3.0. For someone populating and fully utilizing all available m.2 slots it might be an issue.
 
Hmm. Interesting.

I thought the SoC would put out 28 lanes.

Isnt that how Ryzen 1000 and 2000 series CPU's worked?

28 total - 4 for chipset uplink = 24 availaböe direct to CPU? Or did I misunderstand the older designs?

With up to 40 lanes sharing the bandwidth on the chipset, even at Gen4, 4 lanes seems a little anemic. I was hoping they had upped it to 8.

It looks fine to me. They added 4 lanes for a dedicated x4 m.2 slot connected to the CPU, if you need a second m.2 slot, it's in the chipset. It's pretty hard to find room for a third slot on most motherboards.

They had the decency to upgrade the chipset link at the same time, something that usually took Intel 3 generations to get around to.

There's more than enough bandwidth on the chipset for a current-gen Thunderbolt 3 external graphics (32Gbps) plus a current-gen m.2 drive plus USB 3.1 10Gbps slot, running simultaneously.

This happen because once you get past the buffer SLC/MLC available, the performance falls off to under 2GB/s:

sustained.png



They can always dedicate a second x4 slot on a future processor, wherever they get around to releasing Thunderbolt 4.0. But that will be awhile, since it's going to take some serious signal processing to double the speeds on a USB-C cable.

Yeah, you could add more PCIe slots to the south bridge, but with everything you could possibly fit on a standard-sized motherboard, what do they need with more unused lanes?
 
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It looks fine to me. They added 4 lanes for a dedicated x4 m.2 slot connected to the CPU, if you need a second m.2 slot, it's in the chipset. It's pretty hard to find room for a third slot on most motherboards.

They had the decency to upgrade the chipset link at the same time, something that usually took Intel 3 generations to get around to.

There's more than enough bandwidth on the chipset for a current-gen Thunderbolt 3 external graphics (32Gbps) plus a current-gen m.2 drive plus USB 3.1 10Gbps slot, running simultaneously.

This happen because once you get past the buffer SLC/MLC available, the performance falls off to under 2GB/s:

View attachment 162111


They can always dedicate a second x4 slot on a future processor, wherever they get around to releasing Thunderbolt 4.0. But that will be awhile, since it's going to take some serious signal processing to double the speeds on a USB-C cable.

Yeah, you could add more PCIe slots to the south bridge, but with everything you could possibly fit on a standard-sized motherboard, what do they need with more unused lanes?
bunch of x4 slots would be nice for an m.2 nas, or even a rackmount sata nas. just sucks that there's no rdimm support.
 
It looks fine to me. They added 4 lanes for a dedicated x4 m.2 slot connected to the CPU, if you need a second m.2 slot, it's in the chipset. It's pretty hard to find room for a third slot on most motherboards.

They had the decency to upgrade the chipset link at the same time, something that usually took Intel 3 generations to get around to.

There's more than enough bandwidth on the chipset for a current-gen Thunderbolt 3 external graphics (32Gbps) plus a current-gen m.2 drive plus USB 3.1 10Gbps slot, running simultaneously.

This happen because once you get past the buffer SLC/MLC available, the performance falls off to under 2GB/s:

View attachment 162111


They can always dedicate a second x4 slot on a future processor, wherever they get around to releasing Thunderbolt 4.0. But that will be awhile, since it's going to take some serious signal processing to double the speeds on a USB-C cable.

Yeah, you could add more PCIe slots to the south bridge, but with everything you could possibly fit on a standard-sized motherboard, what do they need with more unused lanes?

Less lane sharing/feature sharing. The 4 lanes that either go to M.2 #3, or the PCIe4 x4 slot are the obvious candidate here. Being able to upgrade some of the x1 slots to x4 would be nice too; although after a certain point with it only being an x4 to the CPU you start to end up with Intelesque bottlenecking under heavy load.
 
I assumed it would be PCIe 4 x4 to the M.2 slots and be backwards compatible. The SSD for it doesn't exist yet but that would be a heck of future proof feature. I suppose there is the one x4 slot or splitting the x16 with a graphics card. Less gung ho now about X570.
 
Hmm. Interesting.

I thought the SoC would put out 28 lanes.

Isnt that how Ryzen 1000 and 2000 series CPU's worked?

28 total - 4 for chipset uplink = 24 availaböe direct to CPU? Or did I misunderstand the older designs?

With up to 40 lanes sharing the bandwidth on the chipset, even at Gen4, 4 lanes seems a little anemic. I was hoping they had upped it to 8.


You aren't running SLI and less then 1% of x570 users will be in the future. So take that x8 4.0 slot (which is the same bandwidth as PCI-E x16 3.0 which is PLENTY for any current and next gen card barring some crazy generational leap).

That leaves you the second x8 4.0 link to run any 10 Gbps NIC you want. Add in the fact that the SoC now has double the bandwidth (maybe more) of any current Intel Platform back to the CPU, and there is no issue. You still have a x1 slot for an outdated Sound card if you want it but I know you use a nice external USB DAC like most higher end Audio fiends so that is covered as well.

The real issue (that I hate to see be true) is dropping the Intel NICs for a Realtek and "Killer" LeetOMGLit NIC.
 
You aren't running SLI and less then 1% of x570 users will be in the future. So take that x8 4.0 slot (which is the same bandwidth as PCI-E x16 3.0 which is PLENTY for any current and next gen card barring some crazy generational leap).

That leaves you the second x8 4.0 link to run any 10 Gbps NIC you want. Add in the fact that the SoC now has double the bandwidth (maybe more) of any current Intel Platform back to the CPU, and there is no issue. You still have a x1 slot for an outdated Sound card if you want it but I know you use a nice external USB DAC like most higher end Audio fiends so that is covered as well.

The real issue (that I hate to see be true) is dropping the Intel NICs for a Realtek and "Killer" LeetOMGLit NIC.


Yeah, Realtek and Killer are utter garbage.

With my current board though, I have all onboard lan disabled. Instead I use a dual Intel X520 10 gig server NIC. One of the ports is a direct link to my server. The other goes to my switch.
 
Most decent AM4 boards used Intel NICs- is there a reason for this to change?

Royalties I guess ? I thought the Killer ones were good or at least near on par with Intel ?
Anyway, that's onboard LAN, as usual, if you need better gear up...

That diagram looks promising !
 
Shouldn't all this latest generation stuff support the new 2.5 and 5.0gbs standards over cat5e and cat6?

If I can hit those speeds in the house I wouldn't care a lick about 10gbs.

Well no, 10gbs is still awesome. But why isn't the new tech spreading?
 
Shouldn't all this latest generation stuff support the new 2.5 and 5.0gbs standards over cat5e and cat6?

If I can hit those speeds in the house I wouldn't care a lick about 10gbs.

Well no, 10gbs is still awesome. But why isn't the new tech spreading?

Probably cost and almost everyone I know is using the provided router/modem from their ISP except me. You got enough lanes to add-in an expansion card though.
I wonder what RAID mode they'll support ? This could be a big key factor for me.
 
Shouldn't all this latest generation stuff support the new 2.5 and 5.0gbs standards over cat5e and cat6?

If I can hit those speeds in the house I wouldn't care a lick about 10gbs.

Well no, 10gbs is still awesome. But why isn't the new tech spreading?

Because it's more expensive than 1Gbit :).
 
Source 1

Source 2

"AMD X570 is the company's first in-house design socket AM4 motherboard chipset, with the X370 and X470 chipsets being originally designed by ASMedia. With the X570, AMD hopes to leverage new PCI-Express gen 4.0 connectivity of its Ryzen 3000 Zen2 "Matisse" processors."

"On the AM4 "Valhalla" platform, the SoC puts out a total of 24 PCI-Express gen 4.0 lanes. 16 of these are allocated to PEG (PCI-Express graphics), configurable through external switches and redrivers either as single x16, or two x8 slots. Besides 16 PEG lanes, 4 lanes are allocated to one M.2 NVMe slot. The remaining 4 lanes serve as the chipset bus. With X570 being rumored to support gen 4.0 at least upstream, the chipset bus bandwidth is expected to double to 64 Gbps.

Since it's an SoC, the socket is also wired to LPCIO (SuperIO controller). The processor's integrated southbridge puts out two SATA 6 Gbps ports, one of which is switchable to the first M.2 slot; and four 5 Gbps USB 3.x ports. It also has an "Azalia" HD audio bus, so the motherboard's audio solution is directly wired to the SoC. Things get very interesting with the connectivity put out by the X570 chipset."

Am I seeing this correctly, so up to 3 32Gbps M.2 slots? Two possible from the chipset, one from CPU?

View attachment 162093

According to the diagram one of the M.2 slots is shared with a PCIe expansion slot, but yes you are seeing that correctly.
 
According to the diagram one of the M.2 slots is shared with a PCIe expansion slot, but yes you are seeing that correctly.

3 NVME means no SATA then right ? Is there SATA controller for 1X PCIE 4.0 ?
 
Hopefully some board makers will convert pcie3 to 4, so pcie3 can get the extra bandwidth
 
Hopefully some board makers will convert pcie3 to 4, so pcie3 can get the extra bandwidth

What ? Isn't it backward compatible... you plug Gen 3 into Gen 4 and get double BW ? Maybe I don't understand your statement ? Do you mean update existing boards design ? That would be surprising and counter-productive...
 
Everyone seems to dislike Killer NICs, may I ask why (risking to be flamed lol). I'm pretty sure my Asus route use them and I didn't have any issue (At least they have some feature that works only with those, no clue)
 
What ? Isn't it backward compatible... you plug Gen 3 into Gen 4 and get double BW ? Maybe I don't understand your statement ? Do you mean update existing boards design ? That would be surprising and counter-productive...

Been told that pcie 3.0 devices don't get the extra bandwidth that pcie 4.0 devices do. So if you're usng a pcie 3.0 device using 4 lanes on 4.0. It would give the bandwidth of 3.0 instead of 4.0
 
Been told that pcie 3.0 devices don't get the extra bandwidth that pcie 4.0 devices do. So if you're usng a pcie 3.0 device using 4 lanes on 4.0. It would give the bandwidth of 3.0 instead of 4.0

I was under the impression that it would use it but you might be right, let's wait until someone with more knowledge pitch in :)
 
Everyone seems to dislike Killer NICs, may I ask why (risking to be flamed lol). I'm pretty sure my Asus route use them and I didn't have any issue (At least they have some feature that works only with those, no clue)

Yeah, not sure what the deal is either, have two MSI board (Haswell / Devils Canyon) systems in my home with Onboard Killer E2200 NICs, only a brief driver issue in the last 6 or so yrs, been great overall. A non-issue for me.
 
Yeah, not sure what the deal is either, have two MSI board (Haswell / Devils Canyon) systems in my home with Onboard Killer E2200 NICs, only a brief driver issue in the last 6 or so yrs, been great overall. A non-issue for me.

Is Killer owned by Huawei lol ?
 
People don't like killer because of the rice and I benchmarks it was slower in many cases.
 
3 NVME means no SATA then right ? Is there SATA controller for 1X PCIE 4.0 ?

Yes, if you use 3x NVMe devices you will disable the SATA ports according to the block diagram. There appears to be a PCIe switch for those lanes.
 
Royalties I guess ? I thought the Killer ones were good or at least near on par with Intel ?
Anyway, that's onboard LAN, as usual, if you need better gear up...

That diagram looks promising !

The Intel NICs built into the mid to higher tier 450/470 boards are solid parts and work wonderfully. No driver issues, no random BSODs, no compromised "gaming" software you have to install unlike Killer units (of past anyway)....

Been told that pcie 3.0 devices don't get the extra bandwidth that pcie 4.0 devices do. So if you're usng a pcie 3.0 device using 4 lanes on 4.0. It would give the bandwidth of 3.0 instead of 4.0


A PCI-E 1.X,2,and 3.0 will work fine in a PCI-E slot. You won't Automatically make it a 4.0 part, but it will function perfectly fine.

Now, let's clear up some confusion about the "low" smounts of lanes that you see. Take the GPU lanes, showing x8 4.0. Some would think that their high end 3.0 GPU would only be running at x8 instead of x16. This is true, HOWEVER, PCI-E 4.0 has double the bandwidth of 3.0. So x8 4.0 lanes offer the same raw bandwidth as a x16 3.0 lane.

This is exciting because AMD upgraded the CPU TO SoC backbone to x4 4.0 lanes, vs the x4 3.0 Lanes we have on current AMD/INTEL systems. This gives DOUBLE the bandwidth, which will reduce bottlenecks of your SATA/USB/NVME (off the SoC or "Southbridge").

I hope this forces Intel to follow suit in the future, as z370 is limited to a x4 3.0 uplink, which a single fast NVME drive can saturate.
 
I wanted to further add that PCI-E 4.0 is going to be rather short lived IMO, much like 1.0 boards which were just in the channel when 1.1X boards were announced and quickly hit the channel.

We also have Intel readying the Compute Express Link (CML) which reduces packet overhead, which allows for lower latency) which has been adapted to work over the standard PCI-E 5.0. This will give a massive boost to the CPU-to-SoC backbone.

Once this hits, I think the next step from all 4 large camps (AMD/INTEL/IBM/ARM) is going to 3D stacking this ridding the "Southbridge" completely as a separate piece of silicon.
 
pretty sure the NIC choice falls on the AIB's, so where ever that diagram is from they may be using the killer NIC's on one of their boards.
 
pretty sure the NIC choice falls on the AIB's, so where ever that diagram is from they may be using the killer NIC's on one of their boards.


That's a good point. I knoe some offered the Intel and then a killer NiC as the second choice on the Mobos that had dual NICs. I might be thinking of x399 boards, but I thought some x470 boards had dual NICs.
 
is going to 3D stacking this ridding the "Southbridge" completely as a separate piece of silicon.

Intel already ships Xeon SoCs, basically i7-grade, with dual 10Gbit NICs. AIBs determine how those are exposed, typically as SFP+, but they can do 10Gbase-T as well IIRC. AMD and Intel can easily upgrade the CPU / chipset side of onboard networking from one-gig to multi-gig or ten-gig to lower the cost of the PHY from whomever.
 
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