AdoredTV Analyzes AMD's Epyc Presentation

[AlphaAtlas]

AMD presented their new "Rome" EPYC processors at the New Horizon event earlier this week, and they made some bold claims about the CPU's architecture and performance. The raw live stream has a lot of filler, but AdoredTV posted a great summary and analysis of the new architecture.

Check out the video here.

It's a bad week to be an Intel fanboy.

 

[rtangwai]

That chiplet idea is a great way to get around the latency and balance issues that the Threadripper 2990WX has.

AMD has tried sharing resources before, like the shared floating point in Bulldozer. This is a good way to better distribute resources.

One thing I'm not entirely sure about: if the core usage is low eg. less than half can it allocate extra resources to the individual chiplets like memory controllers? That way on a low thread-count application you could dedicate more resources, making the CPU even more powerful and less wastage of resources.

 

[velusip]

...AMD has tried sharing resources before, like the shared floating point in Bulldozer. This is a good way to better distribute resources.

The distribution of shared resources was poorly skewed in Bulldozer, which lead to serious bottlenecking. It used combined instruction scheduling across cores, which not only hurt IPC and latency, but also hurt all-core utilization for most of the instruction set. AMD learned from this mistake and shortened their pipeline significantly.

One thing I'm not entirely sure about: if the core usage is low eg. less than half can it allocate extra resources to the individual chiplets like memory controllers? That way on a low thread-count application you could dedicate more resources, making the CPU even more powerful and less wastage of resources.

It's possible, but unlikely since it has very little impact overall as it would only really apply when programming highly specific, SIMD-like operations; which is something that shouldn't be assumed by the architecture, nor should be trusted unto the architecture to conceal and optimize on its own.

 

[Sikkyu]

If Zen 2 is fast as fast as AMD says it is(and they are normally pretty conservative), just wait till zen 4 by 2021.

AMD should have a massive advantage in every category.

Its still mind blowing that Rome can fit into a standard Naples socket. I bet the server guys that switched over to AMD are going to love the cheap double core count.

or the 3000 series could potentially go to 16 cores on the AM4 platform with no other upgrade needed.

 

[Chebsy]

I like listening to the guy from adoredTV, he has a funny/sarcastic way of narrating.

The Rome CPU looks like an innovative design, I hope it works out well for AMD. More sales = more research for upcoming products and better competition which is good for us consumers.

 

[Pieter3dnow]

If Zen 2 is fast as fast as AMD says it is(and they are normally pretty conservative), just wait till zen 4 by 2021.

AMD should have a massive advantage in every category.

Its still mind blowing that Rome can fit into a standard Naples socket. I bet the server guys that switched over to AMD are going to love the cheap double core count.

or the 3000 series could potentially go to 16 cores on the AM4 platform with no other upgrade needed.

Even if it seems not so Intel is working double time to fix problems Needless to say but what if AMD can't get scaling to a lower nano meter process right next time the roles could well be reversed. If you look at how complex things are getting it will require a lot more each time you go smaller using these processes.

I like listening to the guy from adoredTV, he has a funny/sarcastic way of narrating.

The Rome CPU looks like an innovative design, I hope it works out well for AMD. More sales = more research for upcoming products and better competition which is good for us consumers.

If that would have worked for Intel we would not have this conversation nothing stopped them of doing the same as AMD is doing now...
Actually not so much just consumers better for the whole ecosystem

 

[andrewaggb]

It'll be interesting to get into those low benchmark results at the end. I understand his reasoning in thinking they are way low from what you would have expected given the higher ipc and double floating point width.

 

[viper1152012]

 

[Lord of Shadows]

AMD is making all the right decisions in the current cloud computing VM datacenter

 

[mbelue]

AMD should have a massive advantage in every category.

That's assuming every generation has as much left to optimize.

There's a good chance one or two generations on 7nm and there won't be much of anything left to optimize.
Then they gotta transition to more exotic materials to get smaller. I expect that shift to take a LONG time.

 

[Sikkyu]

That's assuming every generation has as much left to optimize.

There's a good chance one or two generations on 7nm and there won't be much of anything left to optimize.
Then they gotta transition to more exotic materials to get smaller. I expect that shift to take a LONG time.

its not about optimizations really, although those help.

Its about the fact that amd can slap 8 chiplets that cost very little to make with massive yeids and intel cannot.

Whats to stop amd from doubling the core count again? and then again?

Amd is no longer limited by die size like intel.

its simple numbers, AMD will have more and not only that, amd will also be on par with IPC. Intel wont have anything remotely competitive after rome and the 3k series till end of 2019 or longer.

 

[Nobu]

its not about optimizations really, although those help.

Its about the fact that amd can slap 8 chiplets that cost very little to make with massive yeids and intel cannot.

Whats to stop amd from doubling the core count again? and then again?

Amd is no longer limited by die size like intel.

its simple numbers, AMD will have more and not only that, amd will also be on par with IPC. Intel wont have anything remotely competitive after rome and the 3k series till end of 2019 or longer.

They can't, not without massive increases in cost due to die size increasing, or much more subdued gains in performance due to lack of sufficient throughput in the central die. If they could get that die on a smaller node or optimize it so that it takes up less space on the current node, that'd be different, but I don't see either happening.

They could, of course, make an even bigger package and socket, but there has to be a limit to how ridiculously huge a cpu can be on modern motherboards (except for very specific workloads, like in supercomputers), and we're talking very expensive chips at that point.

 

[KazeoHin]

They can't, not without massive increases in cost due to die size increasing, or much more subdued gains in performance due to lack of sufficient throughput in the central die. If they could get that die on a smaller node or optimize it so that it takes up less space on the current node, that'd be different, but I don't see either happening.

They could, of course, make an even bigger package and socket, but there has to be a limit to how ridiculously huge a cpu can be on modern motherboards (except for very specific workloads, like in supercomputers), and we're talking very expensive chips at that point.

I mean, They could add another 4 chiplets to that arrangement given it's current amount of empty space. They could increase the size of the chiplets 2x and still have plenty of room, too.

 

[Nobu]

I mean, They could add another 4 chiplets to that arrangement given it's current amount of empty space. They could increase the size of the chiplets 2x and still have plenty of room, too.

"or much more subdued gains in performance due to lack of sufficient throughput in the central die", not to mention reduced perf in things which utilize main memory due to insufficient bandwidth on the bus, much higher power and cooling requirement (although not as much as a single monolithic die, probably), and probably other issues they'd be more familiar with than myself.

I'm not saying there aren't other improvements or optimizations they could make, but they can't just plop in more core chips and get performance for (close to) free. There will be trade-offs, and some will be quite significant without probably not insignificant changes to other parts of the CPU.

 

[KazeoHin]

"or much more subdued gains in performance due to lack of sufficient throughput in the central die", not to mention reduced perf in things which utilize main memory due to insufficient bandwidth on the bus, much higher power and cooling requirement (although not as much as a single monolithic die, probably), and probably other issues they'd be more familiar with than myself.

I'm not saying there aren't other improvements or optimizations they could make, but they can't just plop in more core chips and get performance for (close to) free. There will be trade-offs, and some will be quite significant without probably not insignificant changes to other parts of the CPU.

I see where you're coming from. Something we'll probably see in Epyc V3 (or Zen3/4) is an actual 7nm controller die. While efficiency will not be a huge improvement, it will be much smaller OR can fit way more interconnect links on the same sized die. That, or if they double the size of existing chiplets, the controller die wouldn't need to have more IF links, as the number of chiplets would stay the same. pure speculation and I'm by no means any kind of engineer.

 

[Meaker]

I mean, They could add another 4 chiplets to that arrangement given it's current amount of empty space. They could increase the size of the chiplets 2x and still have plenty of room, too.

Not in the existing power envelope.

 

[ole-m]

AMD is making all the right decisions in the current cloud computing VM datacenter

AMD is making the right decision to maximize performance and profit across all platforms.
I found Zen to magical with One die from top to bottom, but had drawbacks...
This is even more scalable but I think :

2-3 I/O chips (Epyc,TR,AM4\Laptop)
No more APU (Dedicated GPU DIE connected to I/O chip)
1 core (Laptop -> Ryzen->TR->Epyc)

My biggest question is what kind of I/O chip will Threadripper run!
The fact that they can make one core on 7nm and use it in all markets, they can have an 8 core in the same power envelope and frequency as raven and still have the IPC to increase per core performance.
8 core 15w laptops with graphics!

 

[bobzdar]

AMD is making the right decision to maximize performance and profit across all platforms.
I found Zen to magical with One die from top to bottom, but had drawbacks...
This is even more scalable but I think :

2-3 I/O chips (Epyc,TR,AM4\Laptop)
No more APU (Dedicated GPU DIE connected to I/O chip)
1 core (Laptop -> Ryzen->TR->Epyc)

My biggest question is what kind of I/O chip will Threadripper run!
The fact that they can make one core on 7nm and use it in all markets, they can have an 8 core in the same power envelope and frequency as raven and still have the IPC to increase per core performance.
8 core 15w laptops with graphics!

And if they get the same power scaling in vega, you're talking 20CUs instead of 10, or gtx 1050 performance in non memory bandwidth limited situations.

I'm also thinking a really nice tr configuration would be two 8c chiplets with 2 Vega (navi?) 22 chiplets if they can feed it with enough ram bandwidth. That'd be a single socket compute monster.