HardOCP News
[H] News
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- Dec 31, 1969
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George Oh has posted leaked six-core Xeon performance information and specs today that are worth checking out. Not sure how long the info will last so get a look while you can.
Reliable sources have reported in the past that Intels Nehalem processor will have three channels of DDR3 memory per CPU versus two channels of DDR2 memory per AMD Barcelona or upcoming Shanghai processor. That would mean that AMDs massive memory bandwidth advantage will turn in to a large memory bandwidth.