Synopsis of G5 Super Cluster @ Virginia Tech ..

Originally posted by lopoetve
And yes, I'm saying that a CPU is only truly 64bit if every portion of the design is done to move 64bits at a time. That's the whole point. So what if you make a 64bit core, if it can only move 8 bits at a time into it to process.
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By this argument, a 386DX processor is a 32-bit CPU while a 386SX processor is not. Or an 8086 is a 16-bit CPU while an 8088 is not.

I do agree that a wider bus is more advantageous -- no argument from me on that. Smaller bus sizes cut costs. In this case, it's 32 less pins, 32 fewer traces on the board (perhaps saving an additional layer or two on the board), etc. Caching can dramatically reduce the penalty hit caused by the smaller bus.

The G5 is 64-bit because it uses 64-bit registers, and operates on those 64-bit numbers to produce 64-bit results. It also happens to use 64-bit addresses.
 
to beat a dead horse with knowledge ive just gained...

G5 = 2 double precision FPUs each capable of 1 fused MADD (multiply-add - commonly used) per clock. x2 processors = 8 GFLOPS per machine.

so for 1100 machines youd have a theoretical peak of 17.2 its at 10 something.

for opteron = 4gflops.

you'd have to be past 100% efficiency to be at the terascales current performance.
 
Someone said that delivery time would have been an issue.

We could have done over 1,000 dually opterons in a month.

www.boxxtech.com

(We do batches of 100 all the time.)
 
Originally posted by Morley
Someone said that delivery time would have been an issue.

We could have done over 1,000 dually opterons in a month.

www.boxxtech.com

(We do batches of 100 all the time.)
Click to expand...

A year ago when they were doing this?
 
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