BIOS: Above 4G Decoding

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wirk

Gawd
Joined
Sep 2, 2014
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There is such PCIE option available in BIOS, normally disabled.

What are the cases when it must be enabled?

Is this related to using many 64-bit PCIE cards at the same time? In particular many graphics cards (not for gaming)?
 
Thank you for the links. Explanations there are not very transparent. If I would have e.g.
4 Titan Z or 6 Titan X in a motherboard with 7 PCIE slots, this would have to be enabled?
 
I believe this is more of older compatibility BIOS issue than newer. All devices configure their Configuration Space; mapping everything for enumeration. All the newer EFI's that have proper option ROM's and 64bit addressing function for EFI 64bit systems should have this enabled by default due to the limitation of the 4GB range (q.v. graphics card memory mapping). This will move the "Hole" to the 64bit range. The EFI setting is usually hidden and on by default with recent, newer, systems since 32bit operating system are not capable of mapping beyond 4GB. The previous systems had this setting disabled by default because some ROM's and device functions were not compatible, and the firmware used (BIOS/EFI) will not know which OS the end user will be using. Much of this should be automatic now, but at times legacy options are in place for particular installations, or issues that arise for the user.

Yes, if you have multiple GPU's you should map the region to the 64bit range. Basically, the option when enabled, will allow a device to be mapped into the 64bit range. If you do more searches for the PCI hole, 3GB limit and such, you should find the answers you are looking for. http://en.wikipedia.org/wiki/PCI_hole
 
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So it seems this is related to the amount of memory which the system has to reserve for graphics cards. Is this reservation amount depending on the size of the VRAM on the graphics card? Or is the 256 MB maximum for one card?
 
It is related to memory mapped I/O for any device. GPU, sound card, NIC, anything that maps a buffer, memory ring, frame buffer, etc will need an area of memory mapped for communication between CPU and device. This relates to the memory in addressable range to the memory on the device. To note, the hole will always exist. When the full 64bit range is utilized-like how 32bit range was-which will take a long time-the "hole" will exist then too.

http://en.wikipedia.org/wiki/Memory-mapped_I/O

http://blogs.technet.com/b/markrussinovich/archive/2008/07/21/3092070.aspx

http://resources.infosecinstitute.c...rchitecture-part-2-pci-express-based-systems/

Not sure if these will help much, but these links will build there information you need to understand memory mapping and remapping of that I/O space to a region in 64bit addressable range. Mainly the third will do this. It is long for reading, but very educational for PCI devices
 
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